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FEDL9845DIGEST-01
1 Semiconductor MSM9845
VOICE SYNTHESIS LSI with on-chip FIFO Memory
Version 3.10, Dec 4, 2000
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
MSM9845 is a Voice Synthesizer LSI with on-chip FIFO memory. A newly developed synthesis algorithm, OKI ADPCM2, promises superb sound quality. The LSI is fully controllable from an external CPU via 16/8-bit bus interface. MSM9845 is an ideal choice for application systems where such non-microchip data storage as CD ROM is used.
FEATURES
* 16/8-bit Bus Interface * On-chip FIFO Memory Capacity : 1024 Bits 16 ms Buffering When Sampling Frequency at 16.0 kHz, 4-bit ADPCM2 and Monaural Playback selected * Synthesis Algorithms for User's Selection 4, 5, 6, 7, 8-bit Oki ADPCM2 4-bit Oki ADPCM 8/16-bit Straight PCM 8-bit Oki Non-Linear PCM * Oscillation Clock Frequency: 16.9344 MHz/24.576 MHz * Sampling Frequency: 11.025 kHz, 22.05 kHz, 44.1 kHz at fOSC = 16.9344 MHz 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz, 48.0 kHz at fOSC = 24.576 MHz * Sound Level Control (8 levels, 0 dB to -21 dB) * Built-in 14-bit D/A Converter * 3 types of Serial Interface for External DAC * Sampling Rate Conversion Function * Packaging: 56-pin Plastic QFP (QFP56-P-910-0.65-2K) Product Code: MSM9845GA
DIFFERENCE BETWEEN MSM9845 AND MSM9844
ITEM SRC MSM9845GA On-Chip FIR Filter MSM9844GA Not On-Chip FIR Filter
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PIN CONFIGURATION (TOP VIEW)
52 lOW 51 DREQL
48 TEST1
47 TEST0
45 TEST2
43 SlOCK
50 DACKL 49 DGND
44 DASD
46 VCK
56 NC
53 NC
55 XT 54 XT
D0 D1 D2 D3 DVDD D4 D5 D6 D7 NC D8 D9 D10 D11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC 15 D12 16 D13 17 D14 18 D15 19 20 21 AGND 22 NC 23 24 25 TEST3 26 NC 27 AOUTL 28
42 41 40 39 38 37 36 35 34 33 32 31 30 29
BUSY D/C CS RD WR FUL/DREQR MID EMP CH/DACKR RESET CBUSY DVDD AVDD AOUTR
NC
DGND
NC
NC : No Connection
56-Pin Plastic QFP
NC
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BLOCK DIAGRAM
AOUTR AOUTL
EMP MID FUL/DREQR CH/DACKR
DAC FIFO
LPF
LPF
DAC
AVDD AGND DVDD DGND
Volume Controller LPF (FIR) Serial Port VCK SIOCK DASD
D15 to D0 WR RD CS D/C BUSY CBUSY RESET DREQL DACKL IOW XT SRC MCU I/F ADPCM2 / ADPCM / PCM Synthesizer
DMA I/F
Timing Controller
TEST0 TEST1 TEST2 TEST3
XT
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PIN DESCRIPTION
Pin Symbol Type Description When 8-bit bus interface selected, you can define, by using a command, these pins as input/output to/from external memory. When no definition made, these pins are input mode. When 16-bit bus interface selected, they are one half of bi-directional data bus for data input/output from/to external micro-controller and memory. D7 to D0 WR RD CS I/O I I I Another half of bi-directional data bus for data input/output from/to external micro-controller and memory and for status output. WRITE pulse input pin. Input "L" pulse before you can enter command and data to D15 to D0 pins. READ pulse input pin. Input "L" pulse before the LSI can output status and data to D15 to D0 pins. With this pin at "L" level, the LSI accepts WRITE or READ pulse input. At "H" level the LSI would not accept WRITE or READ pulse. While this pin being held "H", D15 to D0 pins are enabled to input/output sound data. While this pin being held "L", D7 to D0 pins are enabled to input a command or output status data. Output "L" level during playback/PAUSE operation. Output "L" level when the LSI is ready to accept a command. "H" level output from this pin indicates FIFO memory is empty. You can change this pin to "L" active by a command input. "H" level output from this pin indicates FIFO memory is more than half. 36 MID O During playback, voice synthesis starts when MID changes to "H" level. You can change this pin to "L" active by a command input. This pin outputs a synchro signal for voice data input / output when non-use of FIFO is selected. "H" level output from this pin indicates FIFO memory is full. During playback operation this pin is held "H" and FIFO memory is write -disabled. 37 FUL/ DREQR You can change this pin to "L" active by a command input. O When DMA Transfer and stereo-playback selected by the command input, the output from this pin becomes DMA Transfer request signal. The pin outputs "H" when the right channel FIFO memory is empty. You can change this pin to "L" active by a command input. When stereo-playback selected, write sound data to the right channel FIFO at "H" level, while data to the left channel FIFO at "L" level. When monaural playback selected, keep this pin "L". You can change this pin to "L" active by a command input. When DMA Transfer and stereo-playback selected by the command input, this pin acknowledges the right channel DMA Transfer permission signal. With this pin at "L" level the LSI enabled the IOW pin to accept the signal. You can change this pin to "H" active by a command input. 51 DREQL O Output "H" level to represent DMA Transfer request signal when FIFO gets empty. If stereo-playback selected, the pin outputs "H" level to represent DMA Transfer request signal when the left channel FIFO gets empty.
11 - 14 16 - 19
D15 to D8
I/O
1-4 6-9 38 39 40
41 42 32 35
D/C BUSY CBUSY EMP
I O O O
34
CH/ DACKR
I
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Pin
Symbol
Type
Description DMA Transfer Permission Acknowledgement signal. With this pin at "L" level the LSI enables the IOW pin to accept the signal. When stereo-playback selected, the pin acknowledges DMA Transfer permission signal for the left channel FIFO. You can change this pin to "H" active by a command input. When DMA Transfer is not in use, keep the pin "H". When DMA Transfer selected, the signal to start writing external memory data to the MSM9845 is entered to this pin. When DMA Transfer is not use, keep the pin "H". 16-bit serial data output pin when the external DAC is in use. Synchronizing clock signal for 16-bit serial data input/output when the external DAC is in use. Pins wired to the oscillator. When the external clock is used, input the clock signal to the XT pin and keep the XT pin open. Input/Output the sampling frequency in use. The signal is used as the synchronizing signal when the external DAC is in use. "L" level input to this pin turns the LSI to the initial status. Pins for testing the LSI. Keep these pins "L". The left channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifier to drive a speaker. The right channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifier to drive a speaker. Digital power supply pin. Insert a 0.1F or larger bypass capacitor between this pin and the DGND pin. Digital GND pin. Analog power supply pin. Insert a 0.1F or larger bypass capacitor between this pin and the AGND pin. Analog GND pin.
50
DACKL
I
52 44 43 54 55 46 33 47, 48 45, 26 28 29 5, 31 21, 49 30 22
IOW DASD SIOCK XT XT VCK RESET TEST0, 1 TEST2, 3 AOUTL AOUTR DVDD DGND AVDD AGND
I O I/O I O I/O I I O O -- -- -- --
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG -- Ta = 25C Conditions Rating -0.3 to +7.0 -0.3 to VDD +0.3 571.4 -55 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V) Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD TOP fOSC Conditions DGND = AGND = 0 V -- -- Rating +4.5 to +5.5 -40 to +85 24.576 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = AVDD = +4.5 V to +5.5 V DGND = AGND = 0 V, Ta = -40 to + 85C Parameter "H" Input Voltage "L" Input Voltage "H" Output Voltage "L" Output Voltage "H" Output Voltage "L" Output Voltage "H" Input Current "H" Input Current "L" Input Current "L" Input Current Operating Current Consumption note 1 note 1 note 2 note 2 note 3 note 4 note 3 note 4 Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 IIH1 IIH2 IIL1 IIL2 IDD Conditions -- -- IOH = -40 A IOL = 2 mA IOH = -40 A IOL = 2 mA VIH = VDD VIH = VDD VIL = GND VIL = GND fOSC = 24.576 MHz without load At reset, power down without load Standby Current Consumption IDDS Ta = -40 to +70C At reset, power down without load Ta = +70 to +85C -- -- 50 A -- -- 10 A Min. VDD x 0.85 -- VDD -0.3 -- VDD -0.3 -- -- -- -10 -20 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- VDD x 0.15 -- 0.45 -- 0.8 10 20 -- -- 40 Unit V V V V V V A A A A mA
note 1) note 2) note 3) note 4)
Applies to output pins excluding XT pin. Applies to XT pin. Applies to input pins excluding XT pin. Applies to XT pins .
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APPLICATION CIRCUIT SAMPLE
Data Bus
MEMORY
MSM9845
D15 to D0 DREQL DACKL IOW DREQR
DMA Controller
DACKR
CPU or MCU
RD WR CS D/C
Sample 1 for 16 bit bus interface with DMA Controller
Data Bus
MEMORY
MSM9845
D15 to D0
CPU or MCU
RD WR CS D/C EMP MID FUL
Sample 2 for 16 bit bus interface with External Memory
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PACKAGE DIMENSIONS
(Unit: mm)
QFP56-P-910-0.65-2K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.43 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd.
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